Timing Signal understanding in Xilinx Simulink

I am having some trouble understanding the concept of Timing Signals in Simulink (Xilink Library).

I will explain with an example,

Suppose you have a serial Bitstream and you would like to take the sum of Odd and Even Bit,

So you would probably write Matlab Code something like this:

Data_Bits=[1 2 3 0 4 5 1 2 0 9];

Sum_Bits=[];
for i=1:length(Data_Bits)/2
    Sum_Bits=[Sum_Bits Data_Bits(2*i-1)+Data_Bits(2*i)]
end

Suppose for a moment, we ignore all the optimization and corner cases aside, where this code might not work.

Assuming that we have to implement this in a hardware, the Data_Bits is coming serially, so you basically wait for 2 clock cycles to get 2 input bits and add it and generate the output.

So for every 2 Clock cycles, you have a an output.

So is it possible to manage the Timing Signal in Xilinx so that we have valid output.

So I donot want to have a intermediate result at the output.

How can we achieve that ? I am thinking of using some kind of an enable input with a free running Clock(Counter).

But how do 开发者_如何学编程we manage this while designing a really complicated system ?

I donot have so much experience with Hardware design. So if my question is dangerously bordering SIMPLE and being STUPID, I am sorry for my intelligence.

Thanks for reading

Kiran

---

If you want your output to only change when it is "valid", you use an enabled register at the output pin with the enable signal connected to something which is high for a single clock tick at the same time as the value going into the register is the one you want to present at the output.

In your case, your "valid" signal toggles between '1' and '0' on alternate clock cycles, so you can just use a flipflop with it's output fed back through an inverter. (In davidd's code, you can see this on the line commented with //tflipflop).

If you had a more complex system which is only valid once in n cycles, you can use a counter which resets every n cycles and use the reset pulse as a "valid" signal.

---

Input stream -------------> AddSub -> register -> output stream
Input stream -> register -> AddSub    register
                                      register
                           counter -> register(enable)

add the input stream and the input stream delayed by 1 cycle. use a 1 bit counter (or a T-flip flop) to enable a register on the output of the adder.

Is that what you are looking for?

Also what do you mean by "managing" this while running a complex system? The verilog or vhdl for this construct would be very simple and could be used in place of system generator blocks.

//note: initialization/reset and limit handling is not included and would need to be considered.
always@(posedge clk)
begin
    databits_1dly <= databits;  //create a once cycle delayed version of databits
    sum <= databits_1dly + databits; //adder
    every_other <= !every_other //t flip flop.
    if (every_other)  //invert if you want the other every_other
       sum_every_other <= sum
end