Is There a Way to Autogenerate Dependencies Tree in Makefile?

Abstract question: I'm programming a mid-size C++/C program that's highly modularized. It has a common interface, which allows you to drop in a number of different sources with the same function declarations, but different implementations and get executables with different functionalities.

I'm working out a make system that can handle the building responsibilities. Currently it's able to grab specialized sources based on contents of a configuration file (for the make process) and dump them in a temporary folder with the proper generic names. Now, I only have to compile the project.

The problem is I have a variable number of sources and the headers that the sources depend on can change with the individual implementations. In other words a static makefile won't do the trick.

'1.' Using the Makefile system alone, is there some way to autogenerate the list of objects (.o) files that Main.cpp needs to compile?

I know I could do this by writing a little python script that my makefile calls, which subsequently makes a custom makefile by parsing the c-files examining their dependencies, starting with the base Main.cpp file.

But I didn't want to turn to this hackish solution if there was a more standardized solution or some way to do this within make.

'2.'

If the makefile system is incapable of this, should I go ahead with my custom python script, or is there a more elegant solution?

...............

To be perfectly clear, again I do NOT have a constant list of dependencies/sources/headers/objects and I do NOT want to force my end user to maintain such a list.

I need some way of autogenerate this tree, based on the contents of my C-files.

Apol开发者_如何学Cogies if this is a "dumb" question, I'm relatively new to the world of make -- and like most am self-taught.

Thank you!

Feel free to ask any questions.

FYI, though, my project has too many sources, though, to just post them all and I cannot do so for proprietary/research reasons.

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Yes, if you are using GCC! Here is some of a Makefile I have in a current project (for all real uses, I'll put this under public domain, have fun).

CC=$(CROSS)gcc -c -g -Wall -Werror -ansi -pedantic $(DEFINES) -I./include

%.o: %.c .d/%.d
    # Your build code here

.d/%.d: %.c
    @$(CC) -MM $< -MF $@

-include $(OBJECTS:%.o=.d/%.d)
-include $(LOBJECTS:%.o=.d/%.d)

If I missed something let me know and I'll check my Makefile again.

Note that $(OBJECTS) is a list of objects I want in my binary and $(LOBJECTS) is a list of objects that is being compiled to a static archive. $(OBJECTS) and $(LIB) (which is created by $(LOBJECTS) are then compiled into a final executable. So the whole thing works across multiple builds of different types of objects followed by linking, etc.

Oh yeah, make sure that you mkdir .d or else it will probably fail. You'll want to check in an empty .d directory to your version control.

The only caveat here is that you have to list sources. However, if you want you could set up some little tool to use find to find all your sources for you.

Finally, this can probably be tidied up to be more efficient and more readable by using multiple targets (%.o .d/%d); I'll have to look into that. Thanks for reminding me.

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One way to simplify the build is skip dependencies. Just recompile everything every time. Only if the build has to be done many times, or it takes a "long time", the definition of which depends on the use, and the dependencies change a lot, does it make sense to do a detailed dependency build.