How do I fix shift operator syntax error?

I am trying to compile my code,开发者_高级运维 but I am getting errors when using the arithmetic right shift operator: >>>. Here is the code:

if (from_id_hmic[117:115]==3'b011)
begin
  reg_stat[rt[0]]>>>1'b1; 
end

Here is the error:

Error: E:/Modeltech_pe_edu_10.0/examples/hmic.v(86): near ">>>": syntax error, unexpected >>>

What is my mistake?

---

You have an incomplete Verilog statement. You need to make an assignment. Just trying to perform a shift is insufficient, just as a + 2; is an incomplete statement. You probably want something like this:

result = reg_stat[rt[0]]>>>1'b1;

or perhaps:

reg_stat[rt[0]] >>>= 1'b1; 

>>>= is a "binary arithmetic shift assignment operator" (refer to IEEE Std 1800-2009 "Operators and data types").