Unsigned logic, vector and addition - How?

I'm creating a program counter that is supposed to use only unsigned numbers.

I have 2 STD_LOGIC_VECTOR and a couple of STD_LOGIC. Is there anything I need to do so that they only use unsigned? At the moment I only have library IEEE; use IEEE.STD_LOGIC_1164.ALL;

I also need to increase one of the binary vectors by 1 under certain conditions (as you probably have gues开发者_JS百科sed by now). Would you be so kind to explain how to perform such actions (using unsigned and adding up one) considering one of the vectors is output with 32 bits.

I'm guessing (I tried) Output <= Output + 1; won't do. Oh and I'm using a process.

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In brief, you can add the ieee.numeric_std package to your architecture (library ieee; use ieee.numeric_std.all;) and then do the addition using:

Output <= std_logic_vector(unsigned(Output) + 1);

to convert your std_logic_vector to an unsigned vector, increment it, and finally convert the result back to an std_logic_vector.

Note that if Output is an output port, this won't work because you can't access the value of an output port within the same block. If that is the case, you need to add a new signal and then assign Output from that signal, outside your process.

If you do need to add a signal, it might be simpler to make that signal a different type than std_logic_vector. For example, you could use an integer or the unsigned type above. For example:

architecture foo of bar is
    signal Output_int : integer range 0 to (2**Output'length)-1;
begin
    PR: process(clk, resetn)
    begin
        if resetn='0' then
            Output_int <= 0;
        elsif clk'event and clk='1' then
            Output_int <= Output_int + 1;
        end if;
    end process;

    Output <= std_logic_vector(to_unsigned(Output_int, Output'length));
end foo;

Output_int is declared with a range of valid values so that tools will be able to determine both the size of the integer as well as the range of valid values for simulation. In the declaration of Output_int, Output'length is the width of the Output vector (as an integer), and the "**" operator is used for exponentiation, so the expression means "all unsigned integers that can be expressed with as many bits as Output has".

For example, for an Output defined as std_logic_vector(31 downto 0), Output'length is 32. 2³²-1 is the highest value that can be expressed with an unsigned 32-bit integer. Thus, in the example case, the range 0 to (2**Output'length)-1 resolves to the range 0...4294967295 (2³²=4294967296), i.e. the full unsigned range that can be expressed with 32 bits.

Note that you'll need to add any wrapping logic manually: VHDL simulators will produce an error when you've reached the maximum value and try to increment by one, even if the synthesized logic will cleanly wrap around to 0.