create two elements connecting to one mux 41 and 21

I have big problem because i dont uderstand properly how make my homework. Well i have to make something like this:

http://tomaszewicz.zpt.tele.pw.edu.pl/files/u1/zad4.gif

I have code which create b1 but i dont knwo how to create the second and make them connect to b3.

My code is:

library ieee;
use ieee.std_logic_1164.all;

entity test is
generic(
n : integer := 4
);
port(
a, b, c, d : in std_logic_vector(n-1 downto 0);
s : in 开发者_StackOverflowstd_logic_vector(1 downto 0);
y : out std_logic_vector(n-1 downto 0)
);
end test;



-- przypisanie sekwencyjne - case
architecture arch_mux5 of test is
begin
pr_case: process(a,b,c,d,s)
begin
case s is
when "00" => y <= a;
when "01" => y <= b;
when "10" => y <= c;
when others => y <= d;
end case;
end process;
end arch_mux5;

architecture arch_mux6 of test is
begin
pr_if: process(a,b,c,d,s)
begin
y <= (others => '0'); -- latch jesli zakomentujemy, dlaczego?
if s = "00" then
y <= a;
end if;
if s = "01" then
y <= b;
end if;
if s = "10" then
y <= c;
end if;
if s = "11" then
y <= d;
end if;
end process;
end arch_mux6;

configuration cfg of test is
for arch_mux5
end for;
end cfg;

mux5 and mux6 seems to be the same but in different write method.

---

You have to instantiate those multiplexers, e.g.:

entity top is
  generic (
    n: integer:=4
  );
  port (
    a, b, c, d, e, f, g, h: in std_logic_vector(n-1 downto 0);
    s: in std_logic_vector(2 downto 0);
    y: out std_logic_vector(n-1 downto 0)
  );
end entity top;

architecture struct of top is
  signal t1, t2: std_logic_vector(n-1 downto 0);
  component test is
    generic(
      n : integer := 4
    );
    port (
      a, b, c, d : in std_logic_vector(n-1 downto 0);
      s : in std_logic_vector(1 downto 0);
      y : out std_logic_vector(n-1 downto 0)
    );
  end component test;
  component mux2 is
    generic(
      n : integer := 4
    );
    port (
      a, b : in std_logic_vector(n-1 downto 0);
      s : in std_logic;
      y : out std_logic_vector(n-1 downto 0)
    );
  end component test;
begin
  b1: test
    generic_map (
      n => n
    );
    port map (
      a => a,
      b => b,
      c => c,
      d => d,
      s => s(1 downto 0),
      y => t1
    );
  b2: test
    generic_map (
      n => n
    );
    port map (
      e => a,
      f => b,
      g => c,
      h => d,
      s => s(1 downto 0),
      y => t2
    );
  b3: mux2
    generic_map (
      n => n
    );
    port map (
      a => t1,
      b => t2,
      s => s(2),
      y => y
    );
end architecture struct;

Of course you still have to write the entity+architecture for mux2. I didn't test this code (don't have a VHDL compiler here) but that should at least lead you into the correct direction.

---

Yes, your teacher provided two different ways of implementing the same mux. This is probably done for educational purposes only. You will need to instantiate this mux for b1 and b2.

As @bmk points out, your still need to provide an implementation for b3 and instantiate the three muxes in one top level.