How do I write Verilog testcases in Perl?

I have simple Verilog code and a test bench for which I have to pass the test cases using Perl. I have to write a Perl script of test cases which will receive random i开发者_运维技巧nput. When I execute the Perl script, it will ask for input and whatever I input it will show "the test case has passed".

I tried using Verilog-Perl but it has many .pm files and it is somewhat difficult to utilize them. Can anyone give me hints for this?

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Verilog-Perl is most often used for parsing Verilog files, not for creating testcases.

You could use Perl to generate input stimulus files filled with random numerical data. A simple way to read the files into your testbench is to use the $readmemh Verilog system task during simulation. One benefit is that this avoids recompiling your Verilog code each time you run a new test.

Once the simulation has completed, you could also use Perl to parse the simulation log file to determine and report pass/fail status of the test.

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Check out Test::More which is a very popular testing framework in Perl.