What is wrong in doing this (considering a parallel make)?

I have 2 dirs A and within A I have B.

Makefile in directory A looks like :

include rules.mk            //defines common rules for generating *.o from *.cpp *.c

OBJECTS = test.o \
          B\test1.o \
          B\test2.o

test.lo : $(OBJECTS)
   $(LD) $(LD_OPTS) -o $@ $^
   $(CREATE_CXX_SO)

As is B doesn't have a Makefile defined within it.

Is it mandatory for having Makefiles within the subdirs as well? For s开发者_Go百科erial makes this doesn't seem to pose a problem but while doing parallel makes at times $(LD) tries making conn.lo even before B/test1.o and B/test2.o are compiled.

If what I am doing above is wrong, what are the options that I have?

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I read an excellent article about the recursive use of make at... you guessed it, Recursive Make Considered Harmful. This article details the problems with the distressingly common recursive use of make, and how to build your Makefile such that it can run better and more reliably in parallel.

Or, you can use SCons which works brilliantly.