When and why do you have to use DUT when testing a verilog module?

I just started learning about software test benches for verilog modules. I noticed that when the test bench calls the module, it puts DUT i开发者_开发百科n between the module name and the sensitivity list. What does this mean, and why is it necessary?

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When you instantiate a module, you have to give the instance a name. e.g.

serial_port user_terminal (port mapping);
serial_port debug_port (port mapping);

would instantiate the module serial_port twice, with one of them called user_terminal and one called debug_port.

In your case, DUT is an abbreviation for Device Under Test and is being used as the instance name for your module.

You might like to check out the Doulos Verilog Introduction.