What's wrong with my VHDL testbench?

I've created a testbench 开发者_高级运维to test an adder carry circuit (although it doesn't matter what the circuit is doing)

You can see below that I'm getting 'Error' failures spit out from my testbench.At 261901ps, I show values here in the isim debugger.. test_s(8) and (0) are both '1' and cout is '1'.

Now, my testbench looks like this:

ASSERT (test_s(8) = cout)
    REPORT "Carry out failed for cin = 1!";

So what's wrong? I also tried /= cout just in case.. and I seem to get the same thing. What I want is to say, if test_s MSB (8) is different than cout, then issue an error because that's broken behavior

Cout is std_logic; test_s is std_logic_vector(8 downto 0);

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Your VHDL is correct. You are asserting that test_s(8) should be equal to cout and you report when it is not.

At the cursor on your waveform, test_s(8) is 0 and cout is 1. Your assert is detecting this and reporting it.