Why is there a delay in my VHDL combinational logic within a process?

I'm creating a testbench for combinational logic, where a, b, cin are inputs in to an instantiated unit under test. All that ap开发者_如何学Gopears to be working fine.

However, I'm deriving a test_s signal through addition within my test bench process, and that seems to be strangely delayed. It doesn't matter the duration of my 'wait' statements, I can change the units from ps to ns and the symptoms are the same. What seems to be happening is that a and b set up properly, but test_s doesn't change until a and b change their values. When this happens, test_s actually updates to the previous values of a and b. So at first when a and b become 0, test_s becomes XXXXXXX. Then, when a becomes 1, test_s becomes 0000000 when it should actually be 00000001.

-- Instantiate the Unit Under Test (UUT)
   uut: FastCarry8 PORT MAP (
      a => a,
      b => b,
      cin => cinVec(0), 
      cout => cout
    );

   signal a : std_logic_vector(7 downto 0) := (others => '0');
   signal b : std_logic_vector(7 downto 0) := (others => '0');
   signal cinVec : std_logic_vector(1 downto 0);
   signal test_s : std_logic_vector(8 downto 0);

  -- Stimulus process
  stim_proc: process 
  begin     
  -- hold reset state
  wait for 10 ps;   

    carry_gen: for carry in 0 to 1 loop
        cinVec <= std_logic_vector(to_unsigned(carry, 2));

        b_gen: for j in 0 to 255 loop
            a_gen: for i in 0 to 255 loop

                a <= std_logic_vector(to_unsigned(i, 8));
                b <= std_logic_vector(to_unsigned(j, 8));
                test_s <= std_logic_vector(resize(unsigned(a), test_s'length) + 
                    unsigned(b) + unsigned(cinVec));

                wait for 5ps;

                ASSERT (test_s(8) = cout)
                    REPORT "Carry out failed for cin = 0!";

                wait for 5ps;

            end loop a_gen;
        end loop b_gen;
    end loop carry_gen;

---

Had to put a wait between assignment of a,b and the assignment of test_s since test_s is depending on those signal values.. this was answered privately