Question regarding XST bitstream generation

I have a very simple VHDL module, consisting of a few lines of code. The thing is, when I generate the bitstream, I end up开发者_如何学JAVA with a huge bitstream. The reason for this is, I guess, that XST adds lots of extra information so that the bitstream can run standalone on a FPGA.

However, for my purpose it would be interesting to see the size of the bitstream of the module alone without any extra bits and pieces, just the vaniall module alone. Is there an option in Xilinx ISE 12.1 that allows me to do that?

Many thanks, Richi

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The bitstream contains information for every configurable resource of the device you are targeting regardless of your actual design utilisation. When you program the FPGA the bitfile is clocked into the device, configuring the parts you are not using as well as the ones you are. The size of the bitfile is therefore dictated entirely by the target device.

If you want to see a breakdown of the resources your module is using, take a look at section "Section 14 - Utilization by Hierarchy" in the .mrp file generated by map.

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As Chiggs said, the bitstream is always the same size for each device you're targeting. (You can see this by opening fpga_editor, saving an empty NCD file and converting into a bitstream... still the same size!) Or, in other words, every configuration memory cell must be set (with 0 or 1) on configuration.

But, in fact, you could do what you're asking. It's called dynamic reconfiguration, and for this the tools will generate bitstream pieces that together make an entire bitstream. First you configure the device with a regular bitstream and then you're able to dynamically reconfigure bitstream pieces on top of it while the rest of the FPGA is running normally! (Neat, no?)

Anyway, that's what you asked for, but I'm not sure that's what you wanted... what were you trying to achieve?

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Sorry for jumping into the discussion but I do not think 250KB is a huge bitstream in any way! I use a very small FPGA of 3500 Logic slices and it gives me a bitstream of 3MB. One important thing to consider here. If you are trying to initialize any of your RAMs then the bitstream is going to carry extra bits which are initialization bits of the BRAM Blocks in the FPGA. that can just add additional memory to the bitstream. But on an average, it is the whole FPGA matrix that is getting written with the bits stored in the Offchip/OnChip Flash where the bitfile is stored, So it should not change from run to run.