Verilog doesn't have something like main()?

I understand that modules are essentially like c++ functions. Ho开发者_运维技巧wever, I didn't find something like a main() section that calls those functions. How does it work without a main() section?

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Trying to find (or conceptually force) a main() equivalent in HDL is the wrong way to go about learning HDL -- it will prevent you from making progress. For synthesisable descriptions you need to make the leap from sequential thinking (one instruction running after another) to "parallel" thinking (everything is running all the time). Mentally, look at your code from left to right instead of top to bottom, and you may realize that the concept of main() isn't all that meaningful.

In HDL, we don't "call" functions, we instantiate modules and connect their ports to nets; again, you'll need to change your mental view of the process.

Once you get it, it all becomes much smoother...

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Keep in mind that the normal use of Verilog is modeling/describing circuits. When you apply power, all the circuits start to run, so you need to write your reset logic to get each piece into a stable, usable operating state. Typically you'll include a reset line and do your initialization in response to that.

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Verilog has initial blocks are kinda like main() in C. These are lists of statements that are scheduled to run from time 0. Verilog can have multiple initial blocks though, that are executed concurrently.

always blocks will also work as main() if they've an empty sensitivity list:

always begin // no sensitivity list
   s = 4;
   #10;      // delay statements, or sim will infinite loop
   s = 8;
   #10;
end